!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME	Exuberant Ctags	//
!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
!_TAG_PROGRAM_VERSION	5.5.2	//
AcceptAllPhys	r8169_n.c	/^	AcceptAllPhys = 0x01,$/;"	e	enum:RTL8169_register_content
AcceptBroadcast	r8169_n.c	/^	AcceptBroadcast = 0x08,$/;"	e	enum:RTL8169_register_content
AcceptErr	r8169_n.c	/^	AcceptErr = 0x20,$/;"	e	enum:RTL8169_register_content
AcceptMulticast	r8169_n.c	/^	AcceptMulticast = 0x04,$/;"	e	enum:RTL8169_register_content
AcceptMyPhys	r8169_n.c	/^	AcceptMyPhys = 0x02,$/;"	e	enum:RTL8169_register_content
AcceptRunt	r8169_n.c	/^	AcceptRunt = 0x10,$/;"	e	enum:RTL8169_register_content
CPlusCmd	r8169_n.c	/^	CPlusCmd = 0xE0,$/;"	e	enum:RTL8169_registers
Cfg9346	r8169_n.c	/^	Cfg9346 = 0x50,$/;"	e	enum:RTL8169_registers
Cfg9346_Lock	r8169_n.c	/^	Cfg9346_Lock = 0x00,$/;"	e	enum:RTL8169_register_content
Cfg9346_Unlock	r8169_n.c	/^	Cfg9346_Unlock = 0xC0,$/;"	e	enum:RTL8169_register_content
ChipCmd	r8169_n.c	/^	ChipCmd	= 0x37,$/;"	e	enum:RTL8169_registers
CmdReset	r8169_n.c	/^	CmdReset = 0x10,$/;"	e	enum:RTL8169_register_content
CmdRxEnb	r8169_n.c	/^	CmdRxEnb = 0x08,$/;"	e	enum:RTL8169_register_content
CmdTxEnb	r8169_n.c	/^	CmdTxEnb = 0x04,$/;"	e	enum:RTL8169_register_content
Config0	r8169_n.c	/^	Config0	= 0x51,$/;"	e	enum:RTL8169_registers
Config1	r8169_n.c	/^	Config1	= 0x52,$/;"	e	enum:RTL8169_registers
Config2	r8169_n.c	/^	Config2	= 0x53,$/;"	e	enum:RTL8169_registers
Config3	r8169_n.c	/^	Config3	= 0x54,$/;"	e	enum:RTL8169_registers
Config4	r8169_n.c	/^	Config4	= 0x55,$/;"	e	enum:RTL8169_registers
Config5	r8169_n.c	/^	Config5	= 0x56,$/;"	e	enum:RTL8169_registers
DBG_PRINT	r8169_n.c	92;"	d
DBG_PRINT	r8169_n.c	95;"	d
DEFAULT_MTU	r8169_n.c	119;"	d
DEFAULT_RX_BUF_LEN	r8169_n.c	120;"	d
EORbit	r8169_n.c	/^	EORbit	= 0x40000000,$/;"	e	enum:_DescStatusBit
ERSR	r8169_n.c	/^	ERSR	= 0x36,$/;"	e	enum:RTL8169_registers
ETH_HDR_LEN	r8169_n.c	118;"	d
ETTh	r8169_n.c	116;"	d
ETThReg	r8169_n.c	/^	ETThReg	= 0xEC,$/;"	e	enum:RTL8169_registers
FLASH	r8169_n.c	/^	FLASH	= 0x30,$/;"	e	enum:RTL8169_registers
FSbit	r8169_n.c	/^	FSbit	= 0x20000000,$/;"	e	enum:_DescStatusBit
FullDup	r8169_n.c	/^	FullDup		= 0x01,$/;"	e	enum:RTL8169_register_content
FuncEvent	r8169_n.c	/^	FuncEvent	= 0xF0,$/;"	e	enum:RTL8169_registers
FuncEventMask	r8169_n.c	/^	FuncEventMask	= 0xF4,$/;"	e	enum:RTL8169_registers
FuncForceEvent	r8169_n.c	/^	FuncForceEvent	= 0xFC,$/;"	e	enum:RTL8169_registers
FuncPresetState	r8169_n.c	/^	FuncPresetState	= 0xF8,$/;"	e	enum:RTL8169_registers
IRQ_HANDLED	r8169_n.c	412;"	d
IRQ_NONE	r8169_n.c	411;"	d
InterFrameGap	r8169_n.c	131;"	d
IntrMask	r8169_n.c	/^	IntrMask = 0x3C,$/;"	e	enum:RTL8169_registers
IntrStatus	r8169_n.c	/^	IntrStatus = 0x3E,$/;"	e	enum:RTL8169_registers
LSbit	r8169_n.c	/^	LSbit	= 0x10000000,$/;"	e	enum:_DescStatusBit
LinkChg	r8169_n.c	/^	LinkChg 	= 0x20,$/;"	e	enum:RTL8169_register_content
LinkStatus	r8169_n.c	/^	LinkStatus	= 0x02,$/;"	e	enum:RTL8169_register_content
MAC0	r8169_n.c	/^	MAC0 = 0x0,$/;"	e	enum:RTL8169_registers
MAC_ADDR_LEN	r8169_n.c	111;"	d
MAR0	r8169_n.c	/^	MAR0 = 0x8,$/;"	e	enum:RTL8169_registers
MAX_JUMBO_FRAME_MTU	r8169_n.c	124;"	d
MAX_RX_SKBDATA_SIZE	r8169_n.c	125;"	d
MAX_RX_SKBDATA_SIZE	r8169_n.c	127;"	d
MAX_UNITS	r8169_n.c	100;"	d
MCFG_METHOD_1	r8169_n.c	159;"	d
MCFG_METHOD_2	r8169_n.c	160;"	d
MCFG_METHOD_3	r8169_n.c	161;"	d
MCFG_METHOD_4	r8169_n.c	162;"	d
MODULENAME	r8169_n.c	74;"	d
MultiIntr	r8169_n.c	/^	MultiIntr = 0x5C,$/;"	e	enum:RTL8169_registers
NUM_RX_DESC	r8169_n.c	134;"	d
NUM_TX_DESC	r8169_n.c	133;"	d
OWNbit	r8169_n.c	/^	OWNbit	= 0x80000000,$/;"	e	enum:_DescStatusBit
PCFG_METHOD_1	r8169_n.c	164;"	d
PCFG_METHOD_2	r8169_n.c	165;"	d
PCFG_METHOD_3	r8169_n.c	166;"	d
PCSTimeout	r8169_n.c	/^	PCSTimeout	= 0x4000,$/;"	e	enum:RTL8169_register_content
PFX	r8169_n.c	76;"	d
PHYAR	r8169_n.c	/^	PHYAR	= 0x60,$/;"	e	enum:RTL8169_registers
PHY_1000_CTRL_REG	r8169_n.c	/^	PHY_1000_CTRL_REG = 9,$/;"	e	enum:RTL8169_register_content
PHY_AUTO_NEGO_REG	r8169_n.c	/^	PHY_AUTO_NEGO_REG = 4,$/;"	e	enum:RTL8169_register_content
PHY_Auto_Neco_Comp	r8169_n.c	/^	PHY_Auto_Neco_Comp	= 0x0020,$/;"	e	enum:RTL8169_register_content
PHY_CTRL_REG	r8169_n.c	/^	PHY_CTRL_REG = 0,$/;"	e	enum:RTL8169_register_content
PHY_Cap_1000_Full	r8169_n.c	/^	PHY_Cap_1000_Full	= 0x0200,$/;"	e	enum:RTL8169_register_content
PHY_Cap_100_Full	r8169_n.c	/^	PHY_Cap_100_Full	= 0x0100,$/;"	e	enum:RTL8169_register_content
PHY_Cap_100_Half	r8169_n.c	/^	PHY_Cap_100_Half	= 0x0080,$/;"	e	enum:RTL8169_register_content
PHY_Cap_10_Full	r8169_n.c	/^	PHY_Cap_10_Full		= 0x0040,$/;"	e	enum:RTL8169_register_content
PHY_Cap_10_Half	r8169_n.c	/^	PHY_Cap_10_Half		= 0x0020,$/;"	e	enum:RTL8169_register_content
PHY_Cap_ASYM_PAUSE	r8169_n.c	/^	PHY_Cap_ASYM_PAUSE	= 0x0800,$/;"	e	enum:RTL8169_register_content
PHY_Cap_Null	r8169_n.c	/^	PHY_Cap_Null		= 0x0,$/;"	e	enum:RTL8169_register_content
PHY_Cap_PAUSE	r8169_n.c	/^	PHY_Cap_PAUSE		= 0x0400,$/;"	e	enum:RTL8169_register_content
PHY_Enable_Auto_Nego	r8169_n.c	/^	PHY_Enable_Auto_Nego	= 0x1000,$/;"	e	enum:RTL8169_register_content
PHY_Restart_Auto_Nego	r8169_n.c	/^	PHY_Restart_Auto_Nego	= 0x0200,$/;"	e	enum:RTL8169_register_content
PHY_STAT_REG	r8169_n.c	/^	PHY_STAT_REG = 1,$/;"	e	enum:RTL8169_register_content
PHYstatus	r8169_n.c	/^	PHYstatus = 0x6C,$/;"	e	enum:RTL8169_registers
RTL8169_ALLOC_RXSKB	r8169_n.c	448;"	d
RTL8169_ALLOC_RXSKB	r8169_n.c	452;"	d
RTL8169_DEBUG	r8169_n.c	79;"	d
RTL8169_DRIVER_NAME	r8169_n.c	75;"	d
RTL8169_DYNAMIC_CONTROL	r8169_n.c	85;"	d
RTL8169_FREE_RXSKB	r8169_n.c	449;"	d
RTL8169_FREE_RXSKB	r8169_n.c	453;"	d
RTL8169_HW_FLOW_CONTROL_SUPPORT	r8169_n.c	81;"	d
RTL8169_IOCTL_SUPPORT	r8169_n.c	84;"	d
RTL8169_JUMBO_FRAME_SUPPORT	r8169_n.c	80;"	d
RTL8169_NETIF_RX	r8169_n.c	450;"	d
RTL8169_NETIF_RX	r8169_n.c	454;"	d
RTL8169_READ_GMII_REG	r8169_n.c	/^int RTL8169_READ_GMII_REG( unsigned long ioaddr, int RegAddr )$/;"	f
RTL8169_TIMER_EXPIRE_TIME	r8169_n.c	139;"	d
RTL8169_USE_IO	r8169_n.c	86;"	d
RTL8169_VERSION	r8169_n.c	73;"	d
RTL8169_WRITE_GMII_REG	r8169_n.c	/^void RTL8169_WRITE_GMII_REG( unsigned long ioaddr, int RegAddr, int value )$/;"	f
RTL8169_WRITE_GMII_REG_BIT	r8169_n.c	436;"	d
RTL8169_register_content	r8169_n.c	/^enum RTL8169_register_content {$/;"	g
RTL8169_registers	r8169_n.c	/^enum RTL8169_registers {$/;"	g
RTL_MIN_IO_SIZE	r8169_n.c	137;"	d
RTL_R16	r8169_n.c	147;"	d
RTL_R16	r8169_n.c	155;"	d
RTL_R32	r8169_n.c	148;"	d
RTL_R32	r8169_n.c	156;"	d
RTL_R8	r8169_n.c	146;"	d
RTL_R8	r8169_n.c	154;"	d
RTL_W16	r8169_n.c	144;"	d
RTL_W16	r8169_n.c	152;"	d
RTL_W32	r8169_n.c	145;"	d
RTL_W32	r8169_n.c	153;"	d
RTL_W8	r8169_n.c	143;"	d
RTL_W8	r8169_n.c	151;"	d
RX_DMA_BURST	r8169_n.c	114;"	d
RX_FIFO_THRESH	r8169_n.c	113;"	d
RxBufEmpty	r8169_n.c	/^	RxBufEmpty = 0x01,$/;"	e	enum:RTL8169_register_content
RxCRC	r8169_n.c	/^	RxCRC = 0x00080000,$/;"	e	enum:RTL8169_register_content
RxCfgDMAShift	r8169_n.c	/^	RxCfgDMAShift = 8,$/;"	e	enum:RTL8169_register_content
RxCfgFIFOShift	r8169_n.c	/^	RxCfgFIFOShift = 13,$/;"	e	enum:RTL8169_register_content
RxConfig	r8169_n.c	/^	RxConfig = 0x44,$/;"	e	enum:RTL8169_registers
RxConfigMask	r8169_n.c	/^	u32 RxConfigMask; 	\/* should clear the bits supported by this chip *\/$/;"	m
RxDesc	r8169_n.c	/^struct RxDesc {$/;"	s
RxDescArray	r8169_n.c	/^	struct	RxDesc	*RxDescArray;           \/* Index of 256-alignment Rx Descriptor buffer *\/$/;"	m	struct:rtl8169_private
RxDescStartAddr	r8169_n.c	/^	RxDescStartAddr	= 0xE4,$/;"	e	enum:RTL8169_registers
RxErr	r8169_n.c	/^	RxErr 	= 0x02,$/;"	e	enum:RTL8169_register_content
RxFIFOOver	r8169_n.c	/^	RxFIFOOver 	= 0x40,$/;"	e	enum:RTL8169_register_content
RxFlowCtrl	r8169_n.c	/^	RxFlowCtrl	= 0x20,$/;"	e	enum:RTL8169_register_content
RxMaxSize	r8169_n.c	/^	RxMaxSize = 0xDA,$/;"	e	enum:RTL8169_registers
RxMissed	r8169_n.c	/^	RxMissed = 0x4C,$/;"	e	enum:RTL8169_registers
RxOK	r8169_n.c	/^	RxOK 	= 0x01,$/;"	e	enum:RTL8169_register_content
RxOverflow	r8169_n.c	/^	RxOverflow 	= 0x10,$/;"	e	enum:RTL8169_register_content
RxRES	r8169_n.c	/^	RxRES = 0x00200000,$/;"	e	enum:RTL8169_register_content
RxRUNT	r8169_n.c	/^	RxRUNT= 0x00100000,$/;"	e	enum:RTL8169_register_content
RxRWT	r8169_n.c	/^	RxRWT = 0x00400000,$/;"	e	enum:RTL8169_register_content
Rx_skbuff	r8169_n.c	/^	struct	sk_buff	*Rx_skbuff[NUM_RX_DESC];\/* Receive data buffer *\/$/;"	m	struct:rtl8169_private
SWInt	r8169_n.c	/^	SWInt		= 0x0100,$/;"	e	enum:RTL8169_register_content
SYSErr	r8169_n.c	/^	SYSErr 		= 0x8000,$/;"	e	enum:RTL8169_register_content
TBICSR	r8169_n.c	/^	TBICSR	= 0x64,$/;"	e	enum:RTL8169_registers
TBILinkOK	r8169_n.c	/^	TBILinkOK 	= 0x02000000,$/;"	e	enum:RTL8169_register_content
TBI_ANAR	r8169_n.c	/^	TBI_ANAR = 0x68,$/;"	e	enum:RTL8169_registers
TBI_Enable	r8169_n.c	/^	TBI_Enable	= 0x80,$/;"	e	enum:RTL8169_register_content
TBI_LPAR	r8169_n.c	/^	TBI_LPAR = 0x6A,$/;"	e	enum:RTL8169_registers
TX_DMA_BURST	r8169_n.c	115;"	d
TX_TIMEOUT	r8169_n.c	138;"	d
TxConfig	r8169_n.c	/^	TxConfig = 0x40,$/;"	e	enum:RTL8169_registers
TxDMAShift	r8169_n.c	/^	TxDMAShift = 8,$/;"	e	enum:RTL8169_register_content
TxDesc	r8169_n.c	/^struct TxDesc {$/;"	s
TxDescArray	r8169_n.c	/^	struct	TxDesc	*TxDescArray;           \/* Index of 256-alignment Tx Descriptor buffer *\/$/;"	m	struct:rtl8169_private
TxDescStartAddr	r8169_n.c	/^	TxDescStartAddr	= 0x20,$/;"	e	enum:RTL8169_registers
TxDescUnavail	r8169_n.c	/^	TxDescUnavail	= 0x80,$/;"	e	enum:RTL8169_register_content
TxErr	r8169_n.c	/^	TxErr 	= 0x08,$/;"	e	enum:RTL8169_register_content
TxFlowCtrl	r8169_n.c	/^	TxFlowCtrl	= 0x40,$/;"	e	enum:RTL8169_register_content
TxHDescStartAddr	r8169_n.c	/^	TxHDescStartAddr= 0x28,$/;"	e	enum:RTL8169_registers
TxInterFrameGapShift	r8169_n.c	/^	TxInterFrameGapShift = 24,$/;"	e	enum:RTL8169_register_content
TxOK	r8169_n.c	/^	TxOK 	= 0x04,$/;"	e	enum:RTL8169_register_content
TxPoll	r8169_n.c	/^	TxPoll	= 0x38,$/;"	e	enum:RTL8169_registers
Tx_skbuff	r8169_n.c	/^	struct	sk_buff	*Tx_skbuff[NUM_TX_DESC];\/* Index of Transmit data buffer *\/$/;"	m	struct:rtl8169_private
_1000_Full	r8169_n.c	/^	_1000_Full	= 0x10,$/;"	e	enum:RTL8169_register_content
_1000bpsF	r8169_n.c	/^	_1000bpsF	= 0x10,$/;"	e	enum:RTL8169_register_content
_100_Full	r8169_n.c	/^	_100_Full	= 0x08,$/;"	e	enum:RTL8169_register_content
_100_Half	r8169_n.c	/^	_100_Half	= 0x04,$/;"	e	enum:RTL8169_register_content
_100bps	r8169_n.c	/^	_100bps		= 0x08,$/;"	e	enum:RTL8169_register_content
_10_Full	r8169_n.c	/^	_10_Full	= 0x02,$/;"	e	enum:RTL8169_register_content
_10_Half	r8169_n.c	/^	_10_Half	= 0x01,$/;"	e	enum:RTL8169_register_content
_10bps	r8169_n.c	/^	_10bps		= 0x04,$/;"	e	enum:RTL8169_register_content
_DescStatusBit	r8169_n.c	/^enum _DescStatusBit {$/;"	g
__devinitdata	r8169_n.c	/^static struct pci_device_id rtl8169_pci_tbl[] __devinitdata = {$/;"	v
alloc_rxskb_cnt	r8169_n.c	/^unsigned alloc_rxskb_cnt = 0;$/;"	v
assert	r8169_n.c	90;"	d
assert	r8169_n.c	94;"	d
buf_Haddr	r8169_n.c	/^	u32		buf_Haddr;$/;"	m	struct:RxDesc
buf_Haddr	r8169_n.c	/^	u32		buf_Haddr;$/;"	m	struct:TxDesc
buf_addr	r8169_n.c	/^	u32		buf_addr;$/;"	m	struct:RxDesc
buf_addr	r8169_n.c	/^	u32		buf_addr;$/;"	m	struct:TxDesc
chipset	r8169_n.c	/^	int chipset;$/;"	m	struct:rtl8169_private
cur_rx	r8169_n.c	/^	unsigned long cur_rx;                   \/* Index into the Rx descriptor buffer of next Rx pkt. *\/$/;"	m	struct:rtl8169_private
cur_tx	r8169_n.c	/^	unsigned long cur_tx;                   \/* Index into the Tx descriptor buffer of next Rx pkt. *\/$/;"	m	struct:rtl8169_private
curr_mtu_size	r8169_n.c	/^	int curr_mtu_size;$/;"	m	struct:rtl8169_private
dirty_tx	r8169_n.c	/^	unsigned long dirty_tx;$/;"	m	struct:rtl8169_private
drvinit_fail	r8169_n.c	/^	unsigned char   drvinit_fail;$/;"	m	struct:rtl8169_private
ether_crc	r8169_n.c	/^static inline u32 ether_crc (int length, unsigned char *data)$/;"	f
ethernet_polynomial	r8169_n.c	/^static unsigned const ethernet_polynomial = 0x04c11db7U;$/;"	v
expire_time	r8169_n.c	/^	unsigned long expire_time;$/;"	m	struct:rtl8169_private
hw_rx_pkt_len	r8169_n.c	/^	int hw_rx_pkt_len;$/;"	m	struct:rtl8169_private
ioaddr	r8169_n.c	/^	unsigned long ioaddr;                \/* memory map physical address*\/$/;"	m	struct:rtl8169_private
irqreturn_t	r8169_n.c	/^typedef	int				irqreturn_t;$/;"	t
linkstatus	r8169_n.c	/^	unsigned char   linkstatus;$/;"	m	struct:rtl8169_private
lock	r8169_n.c	/^	spinlock_t lock;                        \/* spin lock flag *\/$/;"	m	struct:rtl8169_private
max_interrupt_work	r8169_n.c	/^static int max_interrupt_work = 20;$/;"	v
mcfg	r8169_n.c	/^	int mcfg;$/;"	m	struct:rtl8169_private
mcfg	r8169_n.c	/^	u8 mcfg;		 \/* depend on RTL8169 docs *\/$/;"	m
media	r8169_n.c	/^static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};$/;"	v
multicast_filter_limit	r8169_n.c	/^static int multicast_filter_limit = 32;$/;"	v
name	r8169_n.c	/^	const char *name;$/;"	m
pcfg	r8169_n.c	/^	int pcfg;$/;"	m	struct:rtl8169_private
pci_dev	r8169_n.c	/^	struct pci_dev *pci_dev;                \/* Index of PCI device  *\/$/;"	m	struct:rtl8169_private
phy_link_down_cnt	r8169_n.c	/^	unsigned long phy_link_down_cnt;$/;"	m	struct:rtl8169_private
r8169_timer	r8169_n.c	/^	rt_timer_t r8169_timer;$/;"	m	struct:rtl8169_private
rt	r8169_n.c	/^	struct r8169_cb_t rt;$/;"	m	struct:rtl8169_private
rt_timer_t	r8169_n.c	/^typedef struct timer_list rt_timer_t;$/;"	t
rtl8169_change_mtu	r8169_n.c	/^static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)$/;"	f
rtl8169_cleanup_module	r8169_n.c	/^module_exit(rtl8169_cleanup_module);$/;"	v
rtl8169_cleanup_module	r8169_n.c	/^static void __exit rtl8169_cleanup_module (void)$/;"	f
rtl8169_close	r8169_n.c	/^static int rtl8169_close (struct net_device *dev)$/;"	f
rtl8169_delete_timer	r8169_n.c	530;"	d
rtl8169_get_stats	r8169_n.c	/^struct net_device_stats *rtl8169_get_stats(struct net_device *dev)$/;"	f
rtl8169_hw_PHY_config	r8169_n.c	/^static void rtl8169_hw_PHY_config (struct net_device *dev)$/;"	f
rtl8169_hw_PHY_reset	r8169_n.c	/^static void rtl8169_hw_PHY_reset(struct net_device *dev)$/;"	f
rtl8169_hw_start	r8169_n.c	/^static void rtl8169_hw_start (struct net_device *dev)$/;"	f
rtl8169_init_board	r8169_n.c	/^static int __devinit rtl8169_init_board ( struct pci_dev *pdev, struct net_device **dev_out, unsigned long *ioaddr_out)$/;"	f
rtl8169_init_module	r8169_n.c	/^module_init(rtl8169_init_module);$/;"	v
rtl8169_init_module	r8169_n.c	/^static int __init rtl8169_init_module (void)$/;"	f
rtl8169_init_one	r8169_n.c	/^static int __devinit rtl8169_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)$/;"	f
rtl8169_init_ring	r8169_n.c	/^static void rtl8169_init_ring (struct net_device *dev)$/;"	f
rtl8169_interrupt	r8169_n.c	/^static void rtl8169_interrupt (int irq, void *dev_instance, struct pt_regs *regs)$/;"	f
rtl8169_intr_mask	r8169_n.c	/^static const u16 rtl8169_intr_mask = LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK ;$/;"	v
rtl8169_mod_timer	r8169_n.c	536;"	d
rtl8169_open	r8169_n.c	/^static int rtl8169_open (struct net_device *dev)$/;"	f
rtl8169_pci_driver	r8169_n.c	/^static struct pci_driver rtl8169_pci_driver = {$/;"	v
rtl8169_phy_timer_t_handler	r8169_n.c	/^void rtl8169_phy_timer_t_handler( void	*timer_data )$/;"	f
rtl8169_private	r8169_n.c	/^struct rtl8169_private {$/;"	s
rtl8169_remove_one	r8169_n.c	/^static void __devexit rtl8169_remove_one (struct pci_dev *pdev)$/;"	f
rtl8169_request_timer	r8169_n.c	520;"	d
rtl8169_rx_config	r8169_n.c	/^static const unsigned int rtl8169_rx_config = (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) | 0x0000000E;$/;"	v
rtl8169_rx_interrupt	r8169_n.c	/^static void rtl8169_rx_interrupt (struct net_device *dev, struct rtl8169_private *priv, unsigned long ioaddr)$/;"	f
rtl8169_set_rx_mode	r8169_n.c	/^static void rtl8169_set_rx_mode (struct net_device *dev)$/;"	f
rtl8169_start_xmit	r8169_n.c	/^static int rtl8169_start_xmit (struct sk_buff *skb, struct net_device *dev)$/;"	f
rtl8169_timer_handler	r8169_n.c	/^void rtl8169_timer_handler( void *timer_data )$/;"	f
rtl8169_tx_clear	r8169_n.c	/^static void rtl8169_tx_clear (struct rtl8169_private *priv)$/;"	f
rtl8169_tx_interrupt	r8169_n.c	/^static void rtl8169_tx_interrupt (struct net_device *dev, struct rtl8169_private *priv, unsigned long ioaddr)$/;"	f
rtl8169_tx_timeout	r8169_n.c	/^static void rtl8169_tx_timeout (struct net_device *dev)$/;"	f
rtl_chip_info	r8169_n.c	/^} rtl_chip_info[] = {$/;"	v
rx_pkt_len	r8169_n.c	/^	int rx_pkt_len;$/;"	m	struct:rtl8169_private
rx_skbuff_dma_addr	r8169_n.c	/^	dma_addr_t rx_skbuff_dma_addr[NUM_RX_DESC];$/;"	m	struct:rtl8169_private
rxdesc_array_dma_addr	r8169_n.c	/^	dma_addr_t rxdesc_array_dma_addr[NUM_RX_DESC];$/;"	m	struct:rtl8169_private
rxdesc_phy_dma_addr	r8169_n.c	/^	dma_addr_t rxdesc_phy_dma_addr;$/;"	m	struct:rtl8169_private
rxdesc_space	r8169_n.c	/^	void *rxdesc_space;$/;"	m	struct:rtl8169_private
sizeof_rxdesc_space	r8169_n.c	/^	int sizeof_rxdesc_space;$/;"	m	struct:rtl8169_private
sizeof_txdesc_space	r8169_n.c	/^	int sizeof_txdesc_space;$/;"	m	struct:rtl8169_private
stats	r8169_n.c	/^	struct net_device_stats stats;          \/* statistics of net device *\/$/;"	m	struct:rtl8169_private
status	r8169_n.c	/^	u32		status;$/;"	m	struct:RxDesc
status	r8169_n.c	/^	u32		status;$/;"	m	struct:TxDesc
tx_pkt_len	r8169_n.c	/^	int tx_pkt_len;$/;"	m	struct:rtl8169_private
txdesc_array_dma_addr	r8169_n.c	/^	dma_addr_t txdesc_array_dma_addr[NUM_TX_DESC];$/;"	m	struct:rtl8169_private
txdesc_phy_dma_addr	r8169_n.c	/^	dma_addr_t txdesc_phy_dma_addr;$/;"	m	struct:rtl8169_private
txdesc_space	r8169_n.c	/^	void *txdesc_space;$/;"	m	struct:rtl8169_private
vlan_tag	r8169_n.c	/^	u32		vlan_tag;$/;"	m	struct:RxDesc
vlan_tag	r8169_n.c	/^	u32		vlan_tag;$/;"	m	struct:TxDesc
